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FN2810.9
April 25, 2007
input register. At each clock, the contents of this register are
summed with the current contents of the accumulator to step to
the new phase. The phase accumulator stepping may be
inhibited by holding ENPHAC high. The phase accumulator
may be loaded with the value in the input register by asserting
LOAD, which zeroes the feedback to the phase accumulator.
The phase adder sums the encoded phase modulation bits
P0-1 and the output of the phase accumulator to offset the
phase by 0°, 90°, 180° or 270°. The two bits are encoded to
produce the phase mapping shown in Table 1. This phase
mapping is provided for direct connection to the in-phase
and quadrature data bits for QPSK modulation.
ROM Section
The ROM section generates the 12-bit sine value from the
13-bit output of the phase adder. The output format is offset
binary and ranges from 001 to FFF hexadecimal, centered
around 800 hexadecimal.
TABLE 1. PHASE MAPPING
P0-1 CODING
P1
P0
PHASE SHIFT (DEGREES)
00
0
01
90
1
0
270
1
180
FIGURE 2A. FREQUENCY LOADING ENABLED BY SFTEN
FIGURE 2B. FREQUENCY LOADING CONTROLLED BY SCLK
FIGURE 3. I/O TIMING
SCLK
SD
SFTEN
MSB/LSB
0
1
2
63
62
61
SCLK
SD
SFTEN
MSB/LSB
0
1
2
63
62
61
CLK
LOAD
TXFR
OUT0-11
1
3
4
6
789
10
11
5
2
NEW
DATA
ENPHAC
SEL_L/M
HSP45102
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